1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices, and more particularly, to a method of manufacturing a semiconductor memory devices, such as DRAM (Dynamic Random Access Memory) devices.
2. Description of the Related Art
When semiconductor devices are miniaturized, line width and the intervals between lines are decreased. The decreased line width and the decreased interval between lines necessitates an increase in the resolution of the lithography process used to manufacture the devices. In general, the enhancements being made in alignment techniques is lagging behind the improvements being made in the resolution. As a result, the minimization of misalignment during manufacture is an important area. This is especially important in the manufacture of semiconductor memory devices that including capacitors, such as DRAMs. In order to increase the effective area of capacitors, bit lines are first formed and then the capacitors are formed. After the formation of the bit lines, buried contacts must be formed. The buried contact electrically connect the source/drain regions of transistors with the storage electrodes of the capacitors. To form these buried contacts, narrow and deep buried contact holes must be formed. It is well known that it is difficult to form contact holes having a high aspect ratio using lithography processes.
In order to minimize the aforementioned limitation, a self-aligned contact (SAC) process is widely used. According to the SAC process, a first insulating layer of oxide layer is formed over a buried contact pad which is located on an impurity region of a semiconductor substrate, for instance, on a source/drain region. Afterwards, bit line stacks, spaced apart from each other by a predetermined interval, are disposed on the first insulating layer. These bit line stacks have a structure where hard mask layers, each consisting of a tungsten (W) layer and a nitride layer, are sequentially stacked. A spacer layer composed of nitride is formed on side walls of the bit line stacks. Thereafter, a second insulating layer of oxide layer is formed to cover the bit line stacks and the space layer. After that, a predetermined mask layer pattern is formed on the second insulating layer, and then a part of the second insulating layer and a part of the first insulating layer are sequentially removed by using the mask layer pattern as an etch mask. In this way, a buried contact hole that partly exposes a surface of the buried contact pad is formed. During the etch step, the hard mask layer of the bit line stack and the spacer layer that are exposed by removing a part of the second insulating layer partly act as the etch mask. Thus, the buried contact hole is aligned by the hard mask layer of the bit line stack and the spacer layer.
In forming the buried contact as above, two factors that greatly influence the device characteristics are the need for sufficient: (1) insulation between the tungsten layer of the bit line stack and the buried contact plug filling the buried contact hole, and (2) contact area between the buried contact plug and the buried contact pad. A large contact area between the buried contact plug and the buried contact pad means that the interval between the spacer layers of the bit line stack should be large and consequently the thickness of the spacer layer should be small. Accordingly, it is required that the thickness of the spacer layer and the interval between adjacent spacer layers of the bit line stack be precise. One reason for this is that the oxide layers of the first and second insulating layers and the nitride layers of the hard mask and the spacer layer are etched together during the etch step for the formation of the buried contact hole. Since the etch selectivity between the oxide layer and the nitride layer is not very high, the nitride layer is etched by a predetermined thickness together with the oxide layer. Thus, it is not easy to maintain the remaining nitride at a desired thickness.